GNU bug report logs - #73837
[PATCH] gnu: iverilog: Update to 12.0.

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Package: guix-patches;

Reported by: Cayetano Santos <csantosb <at> inventati.org>

Date: Wed, 16 Oct 2024 10:21:01 UTC

Severity: normal

Tags: patch

Done: Zheng Junjie <zhengjunjie <at> iscas.ac.cn>

Bug is archived. No further changes may be made.

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From: help-debbugs <at> gnu.org (GNU bug Tracking System)
To: Zheng Junjie <zhengjunjie <at> iscas.ac.cn>
Cc: tracker <at> debbugs.gnu.org
Subject: bug#73837: closed ([PATCH] gnu: iverilog: Update to 12.0.)
Date: Sun, 20 Oct 2024 14:34:03 +0000
[Message part 1 (text/plain, inline)]
Your message dated Sun, 20 Oct 2024 22:32:35 +0800
with message-id <87msiykfp8.fsf <at> iscas.ac.cn>
and subject line Re: [bug#73837] [PATCH] gnu: iverilog: Update to 12.0.
has caused the debbugs.gnu.org bug report #73837,
regarding [PATCH] gnu: iverilog: Update to 12.0.
to be marked as done.

(If you believe you have received this mail in error, please contact
help-debbugs <at> gnu.org.)


-- 
73837: https://debbugs.gnu.org/cgi/bugreport.cgi?bug=73837
GNU Bug Tracking System
Contact help-debbugs <at> gnu.org with problems
[Message part 2 (message/rfc822, inline)]
From: Cayetano Santos <csantosb <at> inventati.org>
To: guix-patches <at> gnu.org
Cc: Cayetano Santos <csantosb <at> inventati.org>
Subject: [PATCH] gnu: iverilog: Update to 12.0.
Date: Wed, 16 Oct 2024 12:19:11 +0200
* gnu/packages/fpga.scm (iverilog): Update to 12.0.

Change-Id: I55c3142aa41b190fef79572576cac6fc02473645
---

Iverilog 12 has a new home page. Update definition as for instructions in there.

 gnu/packages/fpga.scm | 45 +++++++++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index b4ada59b9c..086dcce82a 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -40,6 +40,7 @@ (define-module (gnu packages fpga)
   #:use-module (gnu packages base)
   #:use-module (gnu packages bison)
   #:use-module (gnu packages boost)
+  #:use-module (gnu packages shells)
   #:use-module (gnu packages check)
   #:use-module (gnu packages cmake)
   #:use-module (gnu packages compression)
@@ -106,23 +107,39 @@ (define-public abc
 (define-public iverilog
   (package
     (name "iverilog")
-    (version "11.0")
-    (source (origin
-              (method url-fetch)
-              (uri
-               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
-                              "verilog-" version ".tar.gz"))
-              (sha256
-               (base32
-                "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
+    (version "12.0")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/steveicarus/iverilog")
+             (commit "v12_0")))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
     (build-system gnu-build-system)
     (arguments
-     `(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
-    (native-inputs
-     (list flex bison ghostscript zlib))   ; ps2pdf
-    (home-page "http://iverilog.icarus.com/")
+     (list
+      #:test-target "check"
+      #:make-flags #~(list (string-append "PREFIX="
+                                          #$output))
+      #:phases #~(modify-phases %standard-phases
+                   (delete 'bootstrap)
+                   (add-before 'configure 'autoconf
+                     (lambda _
+                       (invoke "chmod" "+x" "autoconf.sh")
+                       (invoke "./autoconf.sh"))))))
+    (native-inputs (list autoconf bison flex))
+    (inputs (list gawk
+                  gperf
+                  grep
+                  perl
+                  sed
+                  tcsh))
+    (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")
-    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+    (description
+     "Icarus Verilog is a Verilog simulation and synthesis tool.
 It operates as a compiler, compiling source code written in Verilog
 (IEEE-1364) into some target format.
 For batch simulation, the compiler can generate an intermediate form

base-commit: f443f5b0cd77cbbfa70cd915b4082ce32340127e
--
2.46.0



[Message part 3 (message/rfc822, inline)]
From: Zheng Junjie <zhengjunjie <at> iscas.ac.cn>
To: Cayetano Santos <csantosb <at> inventati.org>
Cc: 73837-done <at> debbugs.gnu.org,
 Cayetano Santos via Guix-patches via <guix-patches <at> gnu.org>
Subject: Re: [bug#73837] [PATCH] gnu: iverilog: Update to 12.0.
Date: Sun, 20 Oct 2024 22:32:35 +0800
[Message part 4 (text/plain, inline)]
Z572 <zhengjunjie <at> iscas.ac.cn> writes:

> Cayetano Santos <csantosb <at> inventati.org> writes:
>
>>>mer. 16 oct. 2024 at 20:20, Z572 <zhengjunjie <at> iscas.ac.cn> wrote:
>>
>>> Cayetano Santos via Guix-patches via <guix-patches <at> gnu.org> writes:
>>
>>> It is best to use git send-email, see
>>
>> I’m using send-email (?)
>
> Not sure why some people send emails containing patch that are not sent from their own mailbox
>
> e.g.
> Cayetano Santos via Guix-patches via <guix-patches <at> gnu.org>
>
>
>
>>
>>> And without them, build also success.
>>
>> There is just a couple of warnings:
>>
>>   warning: no binary for interpreter `perl' found in $PATH
>>   warning: no binary for interpreter `csh' found in $PATH
>>
>> I included perl and tcsh to avoid these.
>
> In general, they may be needed for development scripts, so packaging
> does not require them. If packaging fails, you can pay attention to see
> if there is a lack of dependencies here
>
>>
>>> here is patch after the modification.
>>
>> Other than the warnings, fine with me. Any action from my side ?
>
> If there is no problem, I will push it to the warehouse later

push, close.
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This bug report was last modified 213 days ago.

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