Subject: [bug#77273] [PATCH] gnu: verilator: Update to 5.034.

From: Cayetano Santos <[email-masked]>
Date: Wed, 26 Mar 2025 10:49:20 +0100

* gnu/packages/fpga.scm (verilator): Update to 5.034.

Change-Id: I7d61befc8f62736e445bcceca6bfb1e67ef0c186
---

- update
- help2man is a native input, as for the linter
- homepage
- simplify description, too long

 gnu/packages/fpga.scm | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 893e875276..829a16fe93 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -595,21 +595,22 @@ (define-public systemc
 (define-public verilator
   (package
     (name "verilator")
-    (version "5.028")
+    (version "5.034")
     (source
      (origin
        (method git-fetch)
        (uri (git-reference
-             (url "https://github.com/verilator/verilator")
+             (url "https://github.com/verilator/verilator/")
              (commit (string-append "v" version))))
        (file-name (git-file-name name version))
        (sha256
-        (base32 "1q9facgfdwwmf2ax65aznhqmk8qfisq9k5p8wrxrw6qqy38vl0k2"))))
+        (base32 "14alpa2z4fqbbsyx67dz50nqcvfis8pha84545h28xmglrzm13yn"))))
     (native-inputs
      (list autoconf
            automake
            bison
            flex
+           help2man
            gettext-minimal
            python
            ;; And a couple of extras for the test suite:
@@ -617,7 +618,7 @@ (define-public verilator
            gdb/pinned
            which))
     (inputs
-     (list help2man perl python systemc))
+     (list perl python systemc))
     (build-system gnu-build-system)
     (arguments
      '(#:phases
@@ -636,22 +637,13 @@ (define-public verilator
                (lambda ()
                  (display "set auto-load safe-path /"))))))
        #:test-target "test"))
-    ;; #error "Something failed during ./configure as config_build.h is incomplete.
-    ;; Perhaps you used autoreconf, don't." -- so we won't. ^^
-    (home-page "https://www.veripool.org/projects/verilator/")
-    (synopsis "Fast Verilog/SystemVerilog simulator")
+    (home-page "https://www.veripool.org/verilator/")
+    (synopsis "Verilog/SystemVerilog simulator")
     (description
-     "Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
-It ``Verilates'' the specified Verilog or SystemVerilog code by reading it,
+     "Verilator transforms the specified Verilog or SystemVerilog code by reading it,
 performing lint checks, and optionally inserting assertion checks and
 coverage-analysis points.  It outputs single- or multi-threaded @file{.cpp}
-and @file{.h} files, the ``Verilated'' code.
-
-The user writes a little C++/SystemC wrapper file, which instantiates the
-Verilated model of the user’s top level module.  These C++/SystemC files are
-then compiled by a C++ compiler (GCC/Clang/etc.).  The resulting executable
-performs the design simulation.  Verilator also supports linking its generated
-libraries, optionally encrypted, into other simulators.")
+and @file{.h} files.")
     (license license:lgpl3)))
 
 (define-public fftgen

base-commit: 24effa5fc281553a2062f0171cc07ea03db2ecf1
--
2.49.0