GNU bug report logs -
#73717
[PATCH] gnu: Add yosys-clang.
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bug#73717
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(Wed, 09 Oct 2024 07:46:02 GMT)
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Cayetano Santos <csantosb <at> inventati.org>
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(Wed, 09 Oct 2024 07:46:02 GMT)
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Message #5 received at submit <at> debbugs.gnu.org (full text, mbox):
* gnu/packages/fpga.scm (yosys-clang): New variable.
Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da
---
gnu/packages/fpga.scm | 54 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 68f36d501f..5204e041f9 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -224,6 +224,60 @@ (define-public yosys
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
+(define-public yosys-clang
+ (package
+ (inherit yosys)
+ (name "yosys-clang")
+ (arguments
+ (list
+ #:test-target "test"
+ #:make-flags #~(list "CC=clang"
+ "CXX=clang++"
+ (string-append "PREFIX=" #$output))
+ #:phases
+ #~(modify-phases %standard-phases
+ (add-before 'configure 'fix-paths
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* "./backends/smt2/smtio.py"
+ (("\\['z3")
+ (string-append "['" (search-input-file inputs "/bin/z3"))))
+ (substitute* "./kernel/fstdata.cc"
+ (("vcd2fst")
+ (search-input-file inputs "/bin/vcd2fst")))
+ (substitute* '("./passes/cmds/show.cc"
+ "./passes/cmds/viz.cc")
+ (("exec xdot")
+ (string-append "exec " (search-input-file inputs
+ "/bin/xdot")))
+ (("dot -")
+ (string-append (search-input-file inputs "/bin/dot") " -"))
+ (("fuser")
+ (search-input-file inputs "/bin/fuser")))))
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-clang" make-flags)))
+ (add-after 'configure 'use-external-abc
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* '("./Makefile")
+ (("ABCEXTERNAL \\?=")
+ (string-append "ABCEXTERNAL = "
+ (search-input-file inputs "/bin/abc"))))))
+ (add-after 'install 'add-symbolic-link
+ (lambda* (#:key inputs #:allow-other-keys)
+ ;; Previously this package provided a copy of the "abc"
+ ;; executable in its output, named "yosys-abc". Create a
+ ;; symbolic link so any external uses of that name continue to
+ ;; work.
+ (symlink (search-input-file inputs "/bin/abc")
+ (string-append #$output "/bin/yosys-abc"))))
+ (add-after 'install 'wrap
+ (lambda* (#:key inputs #:allow-other-keys)
+ (wrap-program (string-append #$output "/bin/yosys-witness")
+ `("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
+ (inputs
+ (modify-inputs (package-inputs yosys)
+ (append clang)))))
+
(define-public icestorm
(let ((commit "2bc541743ada3542c6da36a50e66303b9cbd2059")
(revision "4"))
base-commit: d44beb9b4ad836781928a0c5667e94c0d6df13f0
--
2.46.0
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guix-patches <at> gnu.org
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bug#73717
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(Sat, 12 Oct 2024 17:56:02 GMT)
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Message #8 received at 73717 <at> debbugs.gnu.org (full text, mbox):
* gnu/packages/fpga.scm (yosys-clang): New variable.
Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da
---
gnu/packages/fpga.scm | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 68f36d501f..042831c024 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -224,6 +224,25 @@ (define-public yosys
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
+(define-public yosys-clang
+ (package
+ (inherit yosys)
+ (name "yosys-clang")
+ (arguments
+ (substitute-keyword-arguments (package-arguments yosys)
+ ((#:make-flags _ #f)
+ #~(list "CC=clang"
+ "CXX=clang++"
+ (string-append "PREFIX=" #$output)))
+ ((#:phases phases)
+ #~(modify-phases #$phases
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-clang" make-flags)))))))
+ (inputs
+ (modify-inputs (package-inputs yosys)
+ (append clang)))))
+
(define-public icestorm
(let ((commit "2bc541743ada3542c6da36a50e66303b9cbd2059")
(revision "4"))
--
2.46.0
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bug#73717
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(Thu, 24 Oct 2024 10:09:02 GMT)
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Message #11 received at 73717 <at> debbugs.gnu.org (full text, mbox):
Hi,
Cayetano Santos <csantosb <at> inventati.org> skribis:
> * gnu/packages/fpga.scm (yosys-clang): New variable.
>
> Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da
[...]
> +(define-public yosys-clang
> + (package
> + (inherit yosys)
> + (name "yosys-clang")
Out of curiosity, why is it necessary to have a Clang-built variant of
yosys? Does that change is feature set?
> + (inputs
Could you add a synopsis, like:
(synopsis "FPGA Verilog RTL synthesizer (Clang variant)")
?
Thanks,
Ludo’.
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(Thu, 24 Oct 2024 13:51:01 GMT)
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Message #14 received at 73717 <at> debbugs.gnu.org (full text, mbox):
>Thu 24 Oct 2024 at 12:07, Ludovic Courtès <ludo <at> gnu.org> wrote:
> Out of curiosity, why is it necessary to have a Clang-built variant of
> yosys? Does that change is feature set?
Performance, cababilities and (usually) different outcomes.
I’m interested on the yosys + ghdl-plugin for synthesis of vhdl code
(not verilog, default in yosys). All these tools come with several
technologies as backends, in order to compare performance, results,
features (code coverage comes to my mind right now), etc.
> Could you add a synopsis, like:
>
> (synopsis "FPGA Verilog RTL synthesizer (Clang variant)")
Sure !
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, guix-patches <at> gnu.org
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bug#73717
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(Tue, 29 Oct 2024 08:57:02 GMT)
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Message #17 received at 73717 <at> debbugs.gnu.org (full text, mbox):
* gnu/packages/fpga.scm (yosys-clang): New variable.
Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da
---
gnu/packages/fpga.scm | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 68f36d501f..5ede463dde 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -224,6 +224,26 @@ (define-public yosys
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
+(define-public yosys-clang
+ (package
+ (inherit yosys)
+ (name "yosys-clang")
+ (arguments
+ (substitute-keyword-arguments (package-arguments yosys)
+ ((#:make-flags _ #f)
+ #~(list "CC=clang"
+ "CXX=clang++"
+ (string-append "PREFIX=" #$output)))
+ ((#:phases phases)
+ #~(modify-phases #$phases
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-clang" make-flags)))))))
+ (inputs
+ (modify-inputs (package-inputs yosys)
+ (append clang)))
+ (synopsis "FPGA Verilog RTL synthesizer (Clang variant)")))
+
(define-public icestorm
(let ((commit "2bc541743ada3542c6da36a50e66303b9cbd2059")
(revision "4"))
base-commit: d44beb9b4ad836781928a0c5667e94c0d6df13f0
--
2.46.0
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guix-patches <at> gnu.org
:
bug#73717
; Package
guix-patches
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(Thu, 21 Nov 2024 10:57:02 GMT)
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Message #20 received at 73717 <at> debbugs.gnu.org (full text, mbox):
user guix
usertag 73717 + patch-review-hackers-list
quit
Reply sent
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Ludovic Courtès <ludo <at> gnu.org>
:
You have taken responsibility.
(Tue, 07 Jan 2025 18:06:03 GMT)
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Notification sent
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Cayetano Santos <csantosb <at> inventati.org>
:
bug acknowledged by developer.
(Tue, 07 Jan 2025 18:06:03 GMT)
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Message #25 received at 73717-done <at> debbugs.gnu.org (full text, mbox):
Cayetano Santos <csantosb <at> inventati.org> skribis:
> * gnu/packages/fpga.scm (yosys-clang): New variable.
>
> Change-Id: Iedbd418adc152c325d106830d9d33b73f01e65da
Finally applied. Thank you, and apologies for the delay!
Ludo’.
bug archived.
Request was from
Debbugs Internal Request <help-debbugs <at> gnu.org>
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internal_control <at> debbugs.gnu.org
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(Wed, 05 Feb 2025 12:24:08 GMT)
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This bug report was last modified 135 days ago.
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