Package: guix-patches;
Reported by: Gary Wong <gtw <at> gnu.org>
Date: Mon, 29 Jan 2024 06:11:02 UTC
Severity: normal
Tags: patch
View this message in rfc822 format
From: Gary Wong <gtw <at> gnu.org> To: 68791 <at> debbugs.gnu.org Subject: [bug#68791] [PATCH 1/3] gnu: yosys: Update to 0.37. Date: Mon, 29 Jan 2024 08:01:07 -0700
* gnu/packages/fpga.scm (yosys): Update to 0.37, and
disable fragile iverilog invocation in arch/run-test.sh.
Change-Id: Ie9ed39ac47fb0a3dde1acd5f699724dc709a00a0
---
gnu/packages/fpga.scm | 162 +++++++++++++++++++++++-------------------
1 file changed, 88 insertions(+), 74 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 13ac1a0b..99841fb6 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -7,6 +7,7 @@
;;; Copyright © 2021 Andrew Miloradovsky <andrew <at> interpretmath.pw>
;;; Copyright © 2022 Christian Gelinek <cgelinek <at> radlogic.com.au>
;;; Copyright © 2022 jgart <jgart <at> dismail.de>
+;;; Copyright © 2024 Gary Wong <gtw <at> gnu.org>
;;;
;;; This file is part of GNU Guix.
;;;
@@ -137,84 +138,97 @@ (define-public iverilog
(define-public yosys
(package
(name "yosys")
- (version "0.26")
- (source (origin
- (method git-fetch)
- (uri (git-reference
- (url "https://github.com/YosysHQ/yosys")
- (commit (string-append "yosys-" version))))
- (sha256
- (base32
- "0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
- (file-name (git-file-name name version))))
+ (version "0.37")
+ (source
+ (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/YosysHQ/yosys")
+ (commit (string-append "yosys-" version))))
+ (sha256
+ (base32 "13f8d02n7fibf77nwfqqlbzfwrpc5qcjx059v04cb76vk9k4bkqp"))
+ (file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
(list
#:test-target "test"
- #:make-flags #~(list "CC=gcc"
- "CXX=g++"
- (string-append "PREFIX=" #$output))
- #:phases
- #~(modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda* (#:key inputs #:allow-other-keys)
- (substitute* "./backends/smt2/smtio.py"
- (("\\['z3")
- (string-append "['" (search-input-file inputs "/bin/z3"))))
- (substitute* "./kernel/fstdata.cc"
- (("vcd2fst")
- (search-input-file inputs "/bin/vcd2fst")))
- (substitute* '("./passes/cmds/show.cc"
- "./passes/cmds/viz.cc")
- (("exec xdot")
- (string-append "exec " (search-input-file inputs
- "/bin/xdot")))
- (("dot -")
- (string-append (search-input-file inputs "/bin/dot") " -"))
- (("fuser")
- (search-input-file inputs "/bin/fuser")))))
- (replace 'configure
- (lambda* (#:key make-flags #:allow-other-keys)
- (apply invoke "make" "config-gcc" make-flags)))
- (add-after 'configure 'use-external-abc
- (lambda* (#:key inputs #:allow-other-keys)
- (substitute* '("./Makefile")
- (("ABCEXTERNAL \\?=")
- (string-append "ABCEXTERNAL = "
- (search-input-file inputs "/bin/abc"))))))
- (add-after 'install 'add-symbolic-link
- (lambda* (#:key inputs #:allow-other-keys)
- ;; Previously this package provided a copy of the "abc"
- ;; executable in its output, named "yosys-abc". Create a
- ;; symbolic link so any external uses of that name continue to
- ;; work.
- (symlink (search-input-file inputs "/bin/abc")
- (string-append #$output "/bin/yosys-abc"))))
- (add-after 'install 'wrap
- (lambda* (#:key inputs #:allow-other-keys)
- (wrap-program (string-append #$output "/bin/yosys-witness")
- `("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
- (native-inputs
- (list bison
- flex
- gawk ; for the tests and "make" progress pretty-printing
- iverilog ; for the tests
- pkg-config
- python
- tcl)) ; tclsh for the tests
- (inputs
- (list abc
- graphviz
- gtkwave
- libffi
- psmisc
- readline
- tcl
- xdot
- z3
- zlib
- python
- python-click))
+ #:make-flags #~(list "CC=gcc" "CXX=g++"
+ (string-append "PREFIX="
+ #$output))
+ #:phases #~(modify-phases %standard-phases
+ (add-before 'configure 'fix-paths
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* "./backends/smt2/smtio.py"
+ (("\\['z3")
+ (string-append "['"
+ (search-input-file inputs "/bin/z3"))))
+ (substitute* "./kernel/fstdata.cc"
+ (("vcd2fst")
+ (search-input-file inputs "/bin/vcd2fst")))
+ (substitute* '("./passes/cmds/show.cc"
+ "./passes/cmds/viz.cc")
+ (("exec xdot")
+ (string-append "exec "
+ (search-input-file inputs "/bin/xdot")))
+ (("dot -")
+ (string-append (search-input-file inputs "/bin/dot")
+ " -"))
+ (("fuser")
+ (search-input-file inputs "/bin/fuser")))))
+ (add-before 'configure 'fix-tests
+ (lambda* (#:key inputs #:allow-other-keys)
+ ;; The arch/run-test.sh script performs a syntax check
+ ;; on the included simulation models, by running
+ ;; iverilog over the model source. Unfortunately this
+ ;; test is prone to false positives, because it is
+ ;; highly sensitive to the version of iverilog in use.
+ ;; Disable iverilog invocation for this test.
+ (substitute* '("./tests/arch/run-test.sh")
+ (("iverilog")
+ "# iverilog"))))
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-gcc" make-flags)))
+ (add-after 'configure 'use-external-abc
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* '("./Makefile")
+ (("ABCEXTERNAL \\?=")
+ (string-append "ABCEXTERNAL = "
+ (search-input-file inputs "/bin/abc"))))))
+ (add-after 'install 'add-symbolic-link
+ (lambda* (#:key inputs #:allow-other-keys)
+ ;; Previously this package provided a copy of the "abc"
+ ;; executable in its output, named "yosys-abc". Create
+ ;; a symbolic link so any external uses of that name
+ ;; continue to work.
+ (symlink (search-input-file inputs "/bin/abc")
+ (string-append #$output "/bin/yosys-abc"))))
+ (add-after 'install 'wrap
+ (lambda* (#:key inputs #:allow-other-keys)
+ (wrap-program (string-append #$output
+ "/bin/yosys-witness")
+ `("GUIX_PYTHONPATH" ":" prefix
+ (,(getenv "GUIX_PYTHONPATH")))))))))
+ (native-inputs (list bison
+ flex
+ gawk ;for the tests and "make" progress pretty-printing
+ iverilog ;for the tests
+ pkg-config
+ python
+ tcl)) ;tclsh for the tests
+ (inputs (list abc
+ bash-minimal
+ graphviz
+ gtkwave
+ libffi
+ psmisc
+ readline
+ tcl
+ xdot
+ z3
+ zlib
+ python
+ python-click))
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")
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