From unknown Wed Jun 18 23:13:56 2025 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) Content-Type: text/plain; charset=utf-8 From: bug#66252 <66252@debbugs.gnu.org> To: bug#66252 <66252@debbugs.gnu.org> Subject: Status: [PATCH 0/3] riscv: Introduce Pseudo NMI Reply-To: bug#66252 <66252@debbugs.gnu.org> Date: Thu, 19 Jun 2025 06:13:56 +0000 retitle 66252 [PATCH 0/3] riscv: Introduce Pseudo NMI reassign 66252 guix-patches submitter 66252 Xu Lu severity 66252 normal tag 66252 patch thanks From debbugs-submit-bounces@debbugs.gnu.org Thu Sep 28 06:16:20 2023 Received: (at submit) by debbugs.gnu.org; 28 Sep 2023 10:16:20 +0000 Received: from localhost ([127.0.0.1]:53080 helo=debbugs.gnu.org) by debbugs.gnu.org with esmtp (Exim 4.84_2) (envelope-from ) id 1qlo49-0004ot-4j for submit@debbugs.gnu.org; Thu, 28 Sep 2023 06:16:20 -0400 Received: from lists.gnu.org ([2001:470:142::17]:50562) by debbugs.gnu.org with esmtp (Exim 4.84_2) (envelope-from ) id 1qlnQ1-0003aA-2V for submit@debbugs.gnu.org; Thu, 28 Sep 2023 05:34:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qlnPh-0004Sn-81 for guix-patches@gnu.org; Thu, 28 Sep 2023 05:34:29 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qlnPe-0000w3-W2 for guix-patches@gnu.org; Thu, 28 Sep 2023 05:34:29 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-690d8c05784so10108320b3a.2 for ; Thu, 28 Sep 2023 02:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1695893660; x=1696498460; darn=gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=EVwUZPjxlXMcD2zjon66oIwZrFvljtzNTeYPJaKrgaM=; b=WWR0OKj8cZ4X72qvf6T5XJRtfO6JR0Afp4AU0BQ/kbK6yT14oRm+WUmAB252b3zbzW 56UltEyGq4hB29UzCNa8QjlBHMzgIFp8+PVHyf0lA7Zcq+Nf/7wF0XjLK9NhTXrbSHrR rHq11iP1CHotMIbBSeFt2wE3Yt2CevNzgU0jqd+n/WTNSnuCE18v+gtE10PSqqxO35kP 7xtLrIiuAqHZ4N9vqje+jkVYIJ7fs/8/jxqN6CXf8d91R3grp+wJMtJ2sYH6z/p2YLTS Kobe0CTpfg5w0nHj41YztMfjFpJIrPXqno4gbWf57IH9FvHX6xTltWGyrhFHr8MDH4a1 5yDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695893660; x=1696498460; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=EVwUZPjxlXMcD2zjon66oIwZrFvljtzNTeYPJaKrgaM=; b=RRk0W3AyW6seH/efK4zBJdcx2GdJgjpuuNBReQVHVfQ6i6LsvTYzZN57naQXi5g45I HWUf1IgFIoeGBAvodCwaIBSRDTrKPv9Jhlcv1kObcc8cCB7xYqMB1A8PhW+ylPvrf6/p F9tV2AvDBc5V/sA3WNOl78zHJpVvjPnj7BOGyGinQNcGvcIsmOmYwLMoCbYTari2nEX/ mo/0rgQqBwDDhefL1XSUfnhM/ZOMS8OkGqUi1unbXzq2EX7BihiEF9KzhkZgk1H/fROu d6qCYzLkx9Y7jBuHoFZdNeb0x3o+GyGquxDVKc0f4IDmh1QzF2+/GbmS87uRfOBRvhhr 42BA== X-Gm-Message-State: AOJu0Yzg5I1uU40ixEJOYTsE7PVmjmGPIYT3iCRE6R7JQN8ZuoXSeO6A Xl2GkaRt9JDr1LmH14TDbypaOsNszr4yiXa5mvE= X-Google-Smtp-Source: AGHT+IFxrANy1sH1nhynZ57bB97eDX/jsrj1msX5k0uCjrFMhD13SHn12t3XleAz5Ip0dSYMcmlcqQ== X-Received: by 2002:a05:6a00:1988:b0:690:d48a:2acc with SMTP id d8-20020a056a00198800b00690d48a2accmr644721pfl.29.1695893659829; Thu, 28 Sep 2023 02:34:19 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([203.208.167.146]) by smtp.gmail.com with ESMTPSA id v16-20020aa78090000000b00690beda6987sm13015203pff.77.2023.09.28.02.34.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 28 Sep 2023 02:34:19 -0700 (PDT) From: Xu Lu To: guix-patches@gnu.org Subject: [PATCH 0/3] riscv: Introduce Pseudo NMI Date: Thu, 28 Sep 2023 17:34:13 +0800 Message-Id: <20230928093413.98747-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=luxu.kernel@bytedance.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Score: 1.0 (+) X-Debbugs-Envelope-To: submit X-Mailman-Approved-At: Thu, 28 Sep 2023 06:16:13 -0400 Cc: Xu Lu X-BeenThere: debbugs-submit@debbugs.gnu.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: debbugs-submit-bounces@debbugs.gnu.org Sender: "Debbugs-submit" X-Spam-Score: -0.0 (/) The existing riscv kernel still lacks a NMI mechanism. It now disables interrupts via per cpu control register CSR_STATUS, the SIE bit of which controls the enablement of all interrupts of whole cpu. This patch series introduces a pseudo NMI mechanism in RISC-V by switching interrupt disable way to another per cpu control register CSR_IE. This register controls the enablement of each seperate interrupt. Every bit of CSR_IE corresponds to a single major interrupt and a clear bit means disablement of corresponding interrupt. The main procedure of implementing pseudo NMI via CSR_IE consists of three steps: Stage1: Make CSR_IE register part of thread context to avoid irq status inconsistence after context switch. Stage2: Switch to CSR_IE masking when disabling irqs. When interrupts are disabled, all bits of CSR_IE corresponding to normal interrupts are cleared while bits corresponding to NMIs are still kept as ones. Stage3: Enable NMIs mannualy during exceptions and normal interrupts as hardware automatically disables all interrupts when trapped into supervisor mode. Xu Lu (3): riscv: Enable NMIs during normal interrupt handling riscv: Request pmu overflow interrupt as NMI riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default arch/riscv/Kconfig | 2 +- arch/riscv/kernel/traps.c | 44 +++++++++++++++++++++++--------- drivers/irqchip/irq-riscv-intc.c | 2 ++ drivers/perf/riscv_pmu_sbi.c | 23 ++++++++++++++--- 4 files changed, 54 insertions(+), 17 deletions(-) base-commit: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c prerequisite-patch-id: 0f865f6b1e0e30e051fd516afeb4cbdf687fa2e3 prerequisite-patch-id: 6632047c24a21a9426d54145f499a9ec4f6fb0c6 prerequisite-patch-id: 681d783ad71fe9770787680cb6d4385ae7a1ac05 prerequisite-patch-id: 1aa352fed255df745c4e47b589405bb9fe932efb prerequisite-patch-id: 579727cfbe5f803335a678b227c31f9ec165df9f prerequisite-patch-id: 9b616129ab18eb41abcdf007ce7d0d49f9a88d36 prerequisite-patch-id: 6c01bc4284a007d3a8b57b919d41380f2786b156 prerequisite-patch-id: f62067b439c1553c96e3462221a16fc52de2accb -- 2.20.1