Hi, Thank you for the patch. I've refactored it to utilize #:test-flags instead adjusting 'check phase and improve it's description by adding more detail from project's README: --8<---------------cut here---------------start------------->8--- modified gnu/packages/electronics.scm @@ -583,18 +583,27 @@ (define-public python-edalize (base32 "1gfysk6wj3mxndyzma604i3y2lkfn1im0bdmzxv5rn4x2nyk68sc")))) (build-system pyproject-build-system) (arguments - `(#:phases (modify-phases %standard-phases - (replace 'check - (lambda* (#:key tests? inputs outputs #:allow-other-keys) - (when tests? - ;; Skip erroneous tests - (invoke "pytest" "tests" "-vv" "-k" - (string-append "not test_gatemate " - "and not test_vivado_edif_netlist " - "and not test_xcelium " "and not test_vcs")))))))) - (native-inputs (list python-setuptools python-wheel python-jinja2 - python-pytest)) - (home-page "https:/test_vivado_edif_netlist/github.com/olofk/edalize/") + (list + #:test-flags + #~(list "-k" (string-join + ;; XXX: Tests failing with assertion not equal, find out + ;; why. + (list "not test_gatemate" + "test_gatemate_minimal" + "test_vcs_tool_options" + "test_vcs_no_tool_options" + "test_vcs_minimal" + "test_vivado_edif_netlist" + "test_vivado_edif_netlist_no_link_design" + "test_xcelium") + " and not ")))) + (native-inputs + (list python-pytest + python-setuptools + python-wheel)) + (propagated-inputs + (list python-jinja2)) + (home-page "https:/github.com/olofk/edalize/") (synopsis "Python Library for interacting with EDA tools") (description "Edalize can create project files for supported tools and run them in modified gnu/packages/electronics.scm @@ -604,11 +604,16 @@ (define-public python-edalize python-wheel)) (propagated-inputs (list python-jinja2)) - (home-page "https:/github.com/olofk/edalize/") + (home-page "https://github.com/olofk/edalize/") (synopsis "Python Library for interacting with EDA tools") (description - "Edalize can create project files for supported tools and run them in -batch or GUI mode.") + "This package implements a functionality to create project files for +supported tools and run them in batch or GUI mode. All EDA tools such as +Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus etc get input HDL +files (Verilog and VHDL) and some tool-specific files (constraint files,memory +initialization files, IP description files etc). Together with the files, +perhaps a couple of Verilog `defines, some top-level parameters/generics or +some tool-specific options are set.") (license license:bsd-2)))0 --8<---------------cut here---------------end--------------->8--- Pushed to master as 8335a6d973c64a89f9a951c638a5d087b7bd8b61. -- Oleg